The First Multi-Gigabit Fully Digital SerDes
About Us
Chronos Tech LLC is a US based company developing game changing IPs and fabric interconnect solutions to enable next-generation intelligent SoCs targeting a wide range of applications, from cloud computing and AI to mobile and automotive, leveraging best in class latency and throughput performance for modern heterogeneous systems across multiple dies
Technology Advantage
Best in class performance and testability
  • 0.6 ns/mm (Based on 10mm link)
  • Lowest latency on the market
  • No clock penalties
  • PPA Calculator available for quick & accurate analysis
  • 5GHz (Based on 7nm TSMC)
  • Link speed not limited by distance
  • Support for Wide data busses
  • 0.1pJ/bit/mm (Based on a 10mm link)
  • Low Power
  • Self clock–gating technology
  • Clock tree removal
  • Substantial saving with AVFS when combined with proprietary "On Die Telemetry"
  • Correct by construction
  • No MD-STA needed
  • Pre & Post Bonding integrated die level testing
  • No clock travelling across dies
Routing Reduction
  • 50% (Based on a large mobile SoC)
  • Bus width reduction
  • Patented compression technology
  • Crosstalk mitigation
Area Reduction
  • 10% (Based on large SoC example)
  • Reduced top level routing -7%
  • Clock tree removal
  • Additional savings inside IPs
  • On Die Telemetry : on chip per-link performance measurement
  • Simplified margining and binning
  • Easier DPM analysis
  • Next Generation AVFS
Ease of Deployment
  • Deployable with standard Digital Flow and Tools
  • Soft IP
  • Automated generation of netlist and constraints
  • Automotive friendly
  • SoC protocol compatible (ARM, RISC-V, etc.)
Safe & Secure
  • Low EMI profile
  • Protect against Differential Power Analysis (DPA) attacks
  • Hardware Trojan detection
  • Soft Failure behavior
Design Space
Our solution covers a wide range of applications:

Cloud AI: Training / Inference

  • Best in Class latency for accelerators
  • Unlimited scalability (Very large dies)
  • Easy integration of next generation Neuromorphic Processing Units (NPU) such as Spiking Neural Network (SNN)

Data Center / HPC

  • High Performance Interconnect
  • High Throughput Low Latency
  • Simplified pipelining and design closure
  • Ideal for High-Speed Switches
  • Unlimited Scalability (no clock limitations)

3D Interconnect

  • High Performance
  • PVT Resilient Interface (ideal for die to die)
  • Correct by construction (No MD-STA needed)
  • Deployable by standard tools and flow
  • Excellent test capability (pre and post Hybrid-Bonding

Automotive / Mobile / Edge-Computing

  • Ideal for complex heterogeneous systems
  • Supports High Throughput
  • Low Latency, Safe and Secure
  • Built-in silicon self test and margining
  • Soft Failure behavior

Arm & RISC-V Based Solutions

  • SoC protocol compatible (AXI, ACE, CHI, Tilelink, OPB, etc.)
  • Tunable PPA per channel enables optimization & flexibility
  • Xplorer (GUI) provides early architectural investigation.
  • Ecosystem ARM partners.

© 2024 Chronos Tech LLC