The Future of Connectivity
Disruptive technology, reduces latency and area, effortless integration of IPs, resilience to PVT
Design SPACE
3D Interconnect
High Performance
PVT Resilient Interface (ideal for die to die)
Correct by construction (No MD-STA needed)
Deployable by standard tools and flow
Excellent test capability (pre and post Hybrid Bond)
Cloud AI: Training / Inference
Best in Class latency for accelerators
Unlimited scalability (Very large dies)
Easy integration of next generation Neuromorphic
Processing Units (NPU) such as Spiking Neural Network (SNN)
Chronos AI Clockless NoC
Data Center / HPC
High Performance Interconnect
High Throughput Low Latency
Simplified pipelining and design closure
Ideal for High Speed Switches
Unlimited Scalability (no clock limitations)
Automotive / Mobile / Edge-Computing
Ideal for complex heterogeneous systems
Supports High Throughput
Low Latency, safe and secure
Built-in silicon self test and margining
Soft Failure behavior
ARM & RISC-V Based Solutions
SoC protocol compatible (AXI, ACE, CHI, Tilelink, OPB, etc.)
Tunable PPA per channel enables optimization & flexibility
Xplorer (GUI) provides early architectural investigation