Disruptive technology, reduces latency and area, effortless integration of IPs, resilience to PVT
Disruptive technology, reduces latency and area, effortless integration of IPs, resilience to PVT
Easy integration of next generation Neuromorphic Processing Units (NPU) such as Spiking Neural Network (SNN)
Low latency memory access for accelerators
Designed for multi-core implementation
Ideal for heterogeneous systems
Low Latency, safe and secure
Built-in silicon self test and margining
Soft Failure behavior
Resilient to PVT variation
Immune to hold-time violation
Yield recovery during early process development
Simplified pipelining and design closure
Validated in advanced FinFET nodes
Clock-less interconnect
Simplified inter-die timing closure
Pin count reduction through patented compression technology
SoC protocol compatible (AXI, ACE, CHI, Tilelink, OPB, etc.)
Tunable PPA per channel enables optimization & flexibility
Xplorer (GUI) provides early architectural investigation