Design SPACE
Machine Learning & Artificial Intelligence
Best in Class latency memory access for accelerators
Easy integration of next generation Neuromorphic
Processing Units (NPU) such as Spiking Neural Network (SNN)
Designed for multi-core implementation
Automotive
Ideal for heterogeneous systems
Low Latency, safe and secure
Built-in silicon self test and margining
Soft Failure behavior
Advance Process Nodes
Resilient to PVT variation
Immune to hold-time violation
Yield recovery during early process development
Simplified pipelining and design closure
Validated in advanced FinFET nodes
3-D Integrated Circuits
Clock-less interconnect
Simplified inter-die timing closure
Pin count reduction through patented compression technology
ARM & RISC-V Based Solutions
SoC protocol compatible (AXI, ACE, CHI, Tilelink, OPB, etc.)
Tunable PPA per channel enables optimization & flexibility
Xplorer (GUI) provides early architectural investigation