Responsible for supporting the development of high-performance custom digital standard-cells to be used in the deployment of Chronos proprietary technology. The engineers will be involved in design and verifications using latest advanced FinFET technology nodes.
1. Hands-on experience with FinFET CMOS technologies (≤ 10nm).
2. Experience with the layout of high performance custom digital standard-cells.
3. Experience with full library characterization and deployment.
4. Experience with Cadence, Mentor and Synopsys suite of design tools (Virtuoso Schematic and Layout, Calibre, etc.).
5. Good understanding of engineering principles, such as matching, shielding, high-speed layout techniques.
6. Ability to work in close collaboration with the designers to achieve a fully optimized layout and with other layout engineers for seamless integration in a digital flow.
7. Good knowledge of device reliability mechanisms, electromigration, latch-up, guard-rings, DNW, IO-Ring building, STI, ESD, parasitics optimization and advanced process effects such as LOD and LDE.
8. Experience with scripting languages such as: skill, perl, python, etc.
9. Self-motivated and creative candidate open to learn new skills and being able to work in a dynamic start-up environment.
10. Number of years of experience: 5+
Responsible for the integration and verification of complex SoC architectures for a broad range of applications.
1. Master’s or equivalent in Electrical Engineering or related & 7-10 yrs experience in job or in related jobs. Ph.D. is a plus.
2. Strong background in logic design and verification with experience in synthesis, static timing analysis, and equivalence checking
3. Solid fundamental knowledge of DFT and digital testing methods including scan compression, BIST, and JTAG
4. Experience in SoC bus architectures, like AMBA (CHI, ACE, AXI), CoreConnect, PSF, etc.
5. Proficiency in developing RTL code in Verilog and/or System Verilog
6. Network-on-Chip (NoC) is a plus.
7. Innovative and willing to brake common BKMs methods and flows.