Responsible for the integration and verification of complex SoC architectures for a broad range of applications.
1. Master’s or equivalent in Electrical Engineering or related & 7-10 yrs exp in job or in related jobs. PhD is a plus.
2. Strong background in logic design and verification with experience in synthesis, static timing analysis, and equivalence checking
3. Solid fundamental knowledge of DFT and digital testing methods including scan compression, BIST, and JTAG
4. Experience in SoC bus architectures, like AMBA, CoreConnect, AXI, Wishbone, PSF, etc.
5. Proficiency in developing SoC RTL code in Verilog and/or System Verilog
6. Network-on-Chip (NoC) is a plus.
7. Innovative and willing to brake common BKMs methods and flows.
Responsible for the physical implementation and sign-off of IPs and top level SoCs.
1. Master degree in Communication Systems, Computer Science or Electrical Engineering with 7-10 years of experience in ASIC Physical Design. PhD is a plus.
2. Strong expertise in the RTL2GDSII flow development or design implementation in leading process technologies
3. Good understanding of synthesis, P&R, CTS, timing convergence, layout closure, UPF based power methodology, etc.
4. Working experience with tools like ICC, Primetime, etc. used in the RTL2GDSII implementation
5. Expertise on high frequency clocking methodologies will be an added plus
6. Good automation skills in PERL, TCL, tool specific scripting on one of the industry leading Place & Route tools
7. Good communication skills and strong motivation for customer support
8. Highly motivated technical expert with good communication and presentation skills.
9. Strong analytical ability and problem solving skills
10. Well versed with timing constraints, STA and timing closure
11. Strong knowledge and experience in Block-level and Full-chip Floor-planning and Physical verification.