Latency -70%
- Based on 12mm link
- Lowest latency on the market
- No clock penalties
- PPA Calculator available for quick & accurate analysis
Routing -50%
- Based on a large mobile SoC
- Bus width reduction
- Patented compression technology
- Crosstalk mitigation
Area -10%
- Based on large SoC example
- Reduced top level routing -7%
- Clock tree removal
- Additional savings inside IPs
Yield +5%
- Resilient to PVT variation
- Poisson model area based ~2%
- No hold-time violations
- Soft Failure behavior
- Beneficial for advanced process development
Power
- Link power comparable to flop based solution
- Self clock–gating technology
- Clock tree removal
- Substantial saving at system level with AVFS when combined with AccuGauge
IP Integration
- Ideal for heterogeneous systems
- Only available solution on the market to natively integrate asynchronous IPs
- Automotive friendly
- SoC protocol compatible (ARM, RISC-V, etc)
- 3D-IC (TSV, etc.)
Test
- AccuGauge: on chip per-link performance measurement
- Simplified margining and binning
- Easier DPM analysis
- Next Generation AVFS
TTM -30%
- Reduce corners up to 90%
- Only slow corners need to be simulated at top level
- Reduced clock tree penalties
- Simplified pipelining and ECO capabilities
Security
- Protect against Differential Power Analysis (DPA) attacks
- Low EMI profile
- Hardware Trojan detection
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