Retis
High Performance, Clockless AI Network on Chip
Chronos Retis
Chronos Retis is a scalable NoC targeting AI application, built upon reliable, clockless Chronos-LLP technology.
It eliminates the need of a large clock distribution network, enabling unlimited scalability, while minimizing power.
Unlike traditional Network on Chip where Latency and Throughput are correlated, this IP is able to decouple the two metrics, enabling unprecedented maximization of performance for the AI accelerators.
The utilization of a truly asynchronous arbiter enable packets to freely flow through the network without the need to wait for the clock, optimizing ques and buffering.
It supports both 2D mesh (5-port Routers) and 3D mesh (7-port Routers) as well as port stubbing for boundary conditions.
For a significant boost in overall system performance, Chronos Retis can connect directly to clockless IP, such as the Chronos-LLP Wormhole or Chronos TimeWarp.
It eliminates the need of a large clock distribution network, enabling unlimited scalability, while minimizing power.
Unlike traditional Network on Chip where Latency and Throughput are correlated, this IP is able to decouple the two metrics, enabling unprecedented maximization of performance for the AI accelerators.
The utilization of a truly asynchronous arbiter enable packets to freely flow through the network without the need to wait for the clock, optimizing ques and buffering.
It supports both 2D mesh (5-port Routers) and 3D mesh (7-port Routers) as well as port stubbing for boundary conditions.
For a significant boost in overall system performance, Chronos Retis can connect directly to clockless IP, such as the Chronos-LLP Wormhole or Chronos TimeWarp.
Benefits
- Better resource Utilization: There is no waiting for the clock, and synchronization only happens at the endpoints. (It can also operate without synchronization with clockless Computing Units)
- Better power: No Clock distribution and automatic AVFS scaling. Each router can operate on a separate Voltage domain.
- Improved latency performance: Computer Unit frequency does not dictate the number of pipeline stages. data flows at the maximum speed that the silicon can operate. Fewer collisions.
- Future Proof: Not limited by OCV and MPW, allowing for unlimited scalability. Native Hybrid-Bonding support for 3D integration.
The Wormhole hard IP is built with a modular approach (bigger data sizes are built in bundles of 32bits) in order to easily reuse/reshape for different data bus sizes.
Redundancy & Self-Healing
Redundancy in the Chronos Wormhole HB 3D-IO is managed through the implementation of extra bundles to ensure high yield and reliability.
This architecture is designed with the constraint that the maximum defect size must be smaller than a single bundle, preventing a single defect from compromising more than four bundles.
To maintain operation despite physical imperfections, the IP features embedded self-healing behavior that automatically re-routes data from damaged bundles to available redundant ones.
This architecture is designed with the constraint that the maximum defect size must be smaller than a single bundle, preventing a single defect from compromising more than four bundles.
To maintain operation despite physical imperfections, the IP features embedded self-healing behavior that automatically re-routes data from damaged bundles to available redundant ones.
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