TimeWarp
Clockless Lowest latency Link Deployable by Standard Tools
Chronos TimeWarp Link Advantage
Chronos TimeWarp link is a clockless high throughput interconnect technology which achieves best in class latency performance: ~365ps/mm including synchronization.
The clockless technology under the hood allows the link to be unaffected by clock degradation enabling staggering performance with no distance limitation.
Chronos proprietary patented technology enables automated deployment of the interconnect as a soft IP, with direct reuse of digital tools and flows and no need to re-train the team (fast TTM).
This clockless technology integrates directly with clocked IPs and has the advantage of a low EMI profile as well reduced cross-talk impact on the signals allowing for tighter routing within the high speed path.
The embedded patented serialization technology allows also for bus width reduction when needed without the need of high speed clocks.
Each Chronos TimeWarp link can use its patented on-chip telemetry to measure real-time on-die link performance.
The clockless technology under the hood allows the link to be unaffected by clock degradation enabling staggering performance with no distance limitation.
Chronos proprietary patented technology enables automated deployment of the interconnect as a soft IP, with direct reuse of digital tools and flows and no need to re-train the team (fast TTM).
This clockless technology integrates directly with clocked IPs and has the advantage of a low EMI profile as well reduced cross-talk impact on the signals allowing for tighter routing within the high speed path.
The embedded patented serialization technology allows also for bus width reduction when needed without the need of high speed clocks.
Each Chronos TimeWarp link can use its patented on-chip telemetry to measure real-time on-die link performance.
Advanced Networking Switch as an Example
In modern high-performance computing (HPC) and AI data centers, the networking architecture is bifurcated into two specialized fabrics to handle distinct traffic profiles.
The Front-End Network (or Management Fabric) typically utilizes standard Ethernet to connect the cluster to external storage, user interfaces, and the internet; it manages tasks like job scheduling, data ingestion, and general system orchestration.
Conversely, the Back-End Network (or Compute Fabric) is a dedicated, ultra-low-latency, high-bandwidth interconnect, designed specifically for inter-node communication. In AI workloads, this back-end fabric is critical for "scale-out" operations, allowing XPUs to exchange massive parameter gradients during training and inference via collective communications like All-Reduce.
By separating these planes, architects ensure that heavy compute-to-compute synchronization doesn't compete for bandwidth with routine data management, minimizing jitter and preventing communication bottlenecks that would otherwise idle expensive processing cores
The Front-End Network (or Management Fabric) typically utilizes standard Ethernet to connect the cluster to external storage, user interfaces, and the internet; it manages tasks like job scheduling, data ingestion, and general system orchestration.
Conversely, the Back-End Network (or Compute Fabric) is a dedicated, ultra-low-latency, high-bandwidth interconnect, designed specifically for inter-node communication. In AI workloads, this back-end fabric is critical for "scale-out" operations, allowing XPUs to exchange massive parameter gradients during training and inference via collective communications like All-Reduce.
By separating these planes, architects ensure that heavy compute-to-compute synchronization doesn't compete for bandwidth with routine data management, minimizing jitter and preventing communication bottlenecks that would otherwise idle expensive processing cores
To maximize performance in modern AI and HPC systems, a primary focus is the aggressive reduction of latency within the back-end network.
This architecture is divided into two critical layers: the Scale-Out Network and the Scale-Up Network.
The Scale-Out Network facilitates communication across different racks with a target delay of less than 10 microseconds, driving a significant industry push toward optical interconnects. This space is governed by the Ultra Ethernet Consortium, which released its first specification in June 2025.
Conversely, the Scale-Up Network handles the high-speed connections between XPUs (Accelerators) within a system, requiring an ultra-low delay of less than 1 microsecond. This domain is managed by the Ethernet Scale-Up Networking (ESUN) group under the Open Compute Project, with its initial specifications released in September 2025.
This architecture is divided into two critical layers: the Scale-Out Network and the Scale-Up Network.
The Scale-Out Network facilitates communication across different racks with a target delay of less than 10 microseconds, driving a significant industry push toward optical interconnects. This space is governed by the Ultra Ethernet Consortium, which released its first specification in June 2025.
Conversely, the Scale-Up Network handles the high-speed connections between XPUs (Accelerators) within a system, requiring an ultra-low delay of less than 1 microsecond. This domain is managed by the Ethernet Scale-Up Networking (ESUN) group under the Open Compute Project, with its initial specifications released in September 2025.
From the OCP Scale-Up Ethernet 1.0 Document specification (shown below), we can see the time budget assigned for the switch (<250ns).
The switch is commonly referred to as Top-of-Rack (ToR) switch, with the Broadcom Tomahawk series serving as a prominent industry example.
These devices are engineered to provide the highest possible port count, a design goal that pushes the System-on-Chip (SoC) to its physical limits. Because the chip's area is primarily determined by the density of high-speed SerDes, these SoCs are usually pin-limited and often reach the maximum reticle size.
In such a massive floorplan (where internal links can exceed 20mm) traditional source-synchronous implementations are becoming unfeasible due to the constraints of the latest process technologies.
For such devices latency remains the most critical metric; any reduction in switch latency translates directly into a measurable boost in overall system performance.
The switch is commonly referred to as Top-of-Rack (ToR) switch, with the Broadcom Tomahawk series serving as a prominent industry example.
These devices are engineered to provide the highest possible port count, a design goal that pushes the System-on-Chip (SoC) to its physical limits. Because the chip's area is primarily determined by the density of high-speed SerDes, these SoCs are usually pin-limited and often reach the maximum reticle size.
In such a massive floorplan (where internal links can exceed 20mm) traditional source-synchronous implementations are becoming unfeasible due to the constraints of the latest process technologies.
For such devices latency remains the most critical metric; any reduction in switch latency translates directly into a measurable boost in overall system performance.
Chronos TimeWarp SoC Link
Chronos TimeWarp revolutionizes high-performance networking by decoupling latency performance from clock degradation across the entire die.
It achieves best-in-class latency performance of approximately 365ps/mm, ensuring that throughput remains unaffected by distance even across very long interconnects.
By automating the deployment of critical SerDes-to-Crossbar and Crossbar-to-SerDes connections—which can span distances greater than 20mm—this solution significantly reduces time-to-market (TTM) compared to traditional, hand-crafted layouts.
Additionally, the technology includes a proprietary on-chip telemetry feature that offers superior testability and power tunability.
Ultimately, Chronos TimeWarp link minimizes XPU-to-XPU interconnect latency, which directly enhances AI training and inference efficiency as well as system scalability.
It achieves best-in-class latency performance of approximately 365ps/mm, ensuring that throughput remains unaffected by distance even across very long interconnects.
By automating the deployment of critical SerDes-to-Crossbar and Crossbar-to-SerDes connections—which can span distances greater than 20mm—this solution significantly reduces time-to-market (TTM) compared to traditional, hand-crafted layouts.
Additionally, the technology includes a proprietary on-chip telemetry feature that offers superior testability and power tunability.
Ultimately, Chronos TimeWarp link minimizes XPU-to-XPU interconnect latency, which directly enhances AI training and inference efficiency as well as system scalability.
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